XCENA RAISES $135M FOR AI MEMORY CHIP TECH

Xcena's funding round highlights growing investment in AI infrastructure optimization. The company's MX1 chip addresses a fundamental bottleneck in large language model inference: the repeated movement of data between memory and processors. Traditional AI systems generate significant overhead when processing queries. Each request triggers what researchers call a "data relay race"—information leaves memory, passes through a CPU for preprocessing, then travels back. This movement consumes time and power. Xcena's approach embeds data orchestration and KV (key-value) cache management directly into memory modules. By performing these operations closer to where data lives, the architecture reduces latency and improves efficiency for inference workloads. The KV cache challenge is particularly acute for large language models. As models generate longer outputs, they accumulate cached key-value pairs that require repeated access. Moving these caches between memory and compute units represents a significant performance tax. The $570 million valuation places Xcena among a crowded field of companies targeting AI infrastructure optimization. Competitors include established players and startups focused on everything from custom processors to memory architectures to software optimization layers. Xcena's Series B brings total funding to undisclosed levels. The round was led by unnamed investors, according to TechCrunch reporting by Kate Park. The company emerges as enterprises and AI providers seek ways to improve inference economics. Running large models at scale remains expensive, making architectural innovations that reduce computational overhead attractive to data center operators and cloud providers. MX1 deployment status and timeline were not disclosed. The funding suggests Xcena plans to accelerate product development and market outreach.